1. Field of the Invention
The present invention relates to a high-performance data processor, and more particularly to a data processor implementing an addressing function for efficient access to a circular buffer.
2. Description of the Background Art
A digital signal processor (DSP) is a special processor for high-speed digital signal processing. Most of the DSPs implement modulo addressing (circular addressing), for efficient utilization of a circular buffer.
The DSP, in general, has more than one independently-accessible data memory or a memory with more than one port in order to perform one or more executions of combined multiply-add instruction in one cycle. Though there are a variety of word sizes, such as 16 bits and 24 bits, in principle, a memory is accessed by one word of given size. When a data processor having a 1-circuit data-memory system performs one or more executions of the multiply-add instruction in one cycle, it must fetch more than one data from the memory in one cycle. Moreover, in a sequential sample-by-sample processing, the data processor performs 1-word access and 2-word access mixedly. No data processor has implemented proper modulo addressing in such a processing as performs 1-word access and 2-word access mixedly.
Further, a typical DSP, for example, as disclosed in U.S. Pat. No. 4,908,748, specifies the size of a circular buffer and judges whether to modify an address after updating based on the address after updating of a pointer and the size of the circular buffer. This judgment on address after updating of the pointer increases the number of executions in one clock-cycle and accordingly hinders improvement in operating frequency for high efficiency.
Another type of DSP judges whether to modify an address based on the address before updating of the pointer. The DSP holds a beginning address (rb) and an ending address (re) to define the range of the circular buffer region. When the postincremented address coincides with the ending address (re), the beginning address (rb) is written back as an updated address. This type of DSP, however, has a problem that the modulo addressing can work only when a 1-increment is made.
In an operation of the DSP, since the region to be accessed with modulo addressing is designated by word address, only 1-word access is allowed with auto-increment or auto-decrement and only one setting for modulo addressing is made. Further, if 2-word access is made to the region with modulo addressing, no other access than 2-word access can be made.
Furthermore, there arises an inconvenience of setting start address and end address since the start address and the end address are reversed between increment and decrement.